Many of today's direct conversion receivers operate in a continuous phase locked mode. Most of these direct conversion receivers have multiple control loops that are active when receiving a message. FIG. 1 is a block diagram of a prior art phase lock loop (PLL) 100 such as would be found in a receiver of a radio, cell phone, or other communication device. PLL 100 is formed of two control loops, a main loop 102 and a secondary loop 104. The interaction between the control loops tends to create a complex environment in which multiple operations, such as DC correction, automatic gain control, and phase locking are all taking place.
In operation, PLL 100 receives a radio frequency (RF) input signal 106 and mixes this signal with a local oscillator (LO) signal 108 at mixer 110 to produce an intermediate frequency (IF) signal 112. The IF signal 112 is filtered through a baseband filter and mixed with a first reference frequency signal (F.sub.REF1) 117 at up mixer 116 to generate an upconverted signal 124. The upconverted signal 124 then splits off into two paths, a high port path in which the signal 124 is demodulated through a demodulator 118, and a low port path which uses a phase detector 120 and equalization circuit 130 to extract low frequency modulation from the signal 124. During operation in phase locked mode the main loop 102 tracks out low frequency components of the modulation, and it is therefore necessary to extract these low frequency components from the phase detector output 128 and equalize the two modulation paths through the equalization circuit 130 and summer 132 port to produce a demodulated signal 134.
The phase detector 120 compares a second reference frequency (F.sub.REF2) 122 to the upconverted signal 124 to produce an output signal having sufficient current to drive a main loop VCO 126. Ideally, the phase detector output 128 would feed the main VCO 126 directly, but one of the problems with this prior art PLL is that the main VCO tends to drift off frequency thereby preventing the secondary loop 104 from locking. To compensate for the drift, a reference frequency automatic tuning circuit 136 is used to periodically center the frequency of the main VCO 126. The reference frequency automatic tuning circuit 136 provides an offset current to correct for the offset of the frequency of the main VCO 126.
The reference frequency automatic tuning circuit 136 used in PLL 100 tunes the main VCO 126 to a precise predetermined frequency. Reference frequency automatic tuning circuit 136 operates by tuning the main VCO 126 to that predetermined frequency and then storing the resulting correction voltage digitally. When the main VCO 126 is placed back in the main phase locked loop the stored correction voltage is applied to the main VCO, guaranteeing the receiver is tuned on frequency and the make tolerance of the VCO has been compensated. In short, the prior art concept is that the newly reconfigured loop uses another reference and centers the VCO about that reference.
Within secondary loop 104, the main VCO output is mixed with the first LO 108 at mixer 138 to produce a second intermediate frequency (IF) signal 139. The IF signal 139 drives another phase detector 140 which controls a secondary VCO 142. The secondary loop 104 determines the first LO injection frequency 108. The combination of the main loop and secondary loop keeps the receiver phase locked to the incoming RF signal.
Phase locking the receiver 100 to the input signal 106 causes the modulation to be tracked out requiring the use of the equalization circuit 130 and summer 132. Operating in phase locked mode also produces poor group delay characteristics which can be troublesome certain types of data reception. The presence of strong adjacent channel signals can also cause the main loop to attempt to lock on the adjacent channel. This can result in the loop becoming indecisive and switching between the desired signal and the adjacent channel to the point that the desired signal becomes effectively lost in the resulting noise. It would therefore be beneficial to simplify the system and eliminate the need for the equalization portion of the circuit.
Accordingly, there is a need for an improved receiver circuit with reduced complexity, while maintaining reliable calibrated tuning conditions.